This invention relates to a clock period sensing circuit and, more particularly, to a clock delay sensing circuit capable of sensing delay and finely adjusting the same.
Examples of conventional clock delay sensing circuits include a series of sensing circuits comprising a series of inverters, and means for sensing delay from the number of stages of a ring oscillator. For example, as shown in FIG. 10, there is known an arrangement in which a period sensing circuit 206 comprises a ring oscillator of a fixed number of stages and a counter, in which the oscillation frequency of the ring oscillator in the period of an input clock is counted by the counter to sense the clock period.
Further, FIG. 11 illustrates an example of the construction of a synchronous delay circuit according to the prior art. This circuit has as its basic components a first delay circuit line 901 for measuring delay (xe2x80x9cmeasuring delay linexe2x80x9d) and a second delay circuit line 902 for reconstructing delay (xe2x80x9csynchronizing delay linexe2x80x9d), the direction of signal propagation of the latter being the opposite of the former. The output end of the second delay circuit line 902 is connected to an output buffer (having a delay time td2), and a transfer control circuit 903 is provided between the first delay circuit line 901 and second delay circuit line 902. The transfer control circuit 903 turns on upon receiving an output from an input buffer 904. A dummy delay circuit 906 having a delay time td1+td2 is inserted between an output end of the input buffer 904 and an input end of the first delay circuit line 901.
An input clock signal enters the first delay circuit line 901 from the input buffer 904 and propagates through the first delay circuit line 901 by the time the next pulse enters following the clock signal period (tCK). At the moment the next pulse enters, the transfer control circuit 903 turns on so that a pulse that has propagated through the first delay circuit line 901 over a period of time equal to (tCKxe2x88x92td1xe2x88x92td2) enters the second delay circuit line 902 from this position, propagates through and is output from the second delay circuit line 902 over the time period (tCKxe2x88x92td1xe2x88x92td2) of propagation through the first delay circuit line 901. The pulse is output via an output buffer 905 (whose delay time is td2). Thus, a signal delayed by 2 tCK from the input In is output at an output terminal Out, where [input buffer (td1)]+[delay circuit (td1+td2)]+{first and second delay circuits [2xc3x97(tCKxe2x88x92td1xe2x88x92td2)]}+[output buffer (td2)]=2 tCK.
In this arrangement of the conventional delay sensing circuit comprising a series of inverters in which the inverter is a unit delay circuit, the unit of delay is decided by the propagation delay time of one inverter stage. Consequently, if the clock period in a subsequent stage is to be finely adjusted, it is required that the unit of delay used in coarse adjustment be changed over at the ends of the operating range. The reason for this is that there is no overlapping of operating ranges in terms of the individual units of delay.
Accordingly, it is an object of the present invention to provide a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc. It is another object of the present invention to provide a clock period sensing circuit in which it is possible to broaden the operating range of phase adjustment and frequency multiplier circuits, etc., particularly allowing performing coarse period adjustment in advance.
According to a first aspect of the present invention, the foregoing object is attained by providing a clock period sensing circuit comprising: a plurality of parallel connected delay sensing circuits having slightly overlapping operating ranges and different centers of operation, wherein a clock signal is passed through the plurality of delay sensing circuits, and the period of the clock is sensed using a signal which identifies delay sensing circuits through which the clock signal has passed and delay sensing circuits through which the clock signal has not passed.
According to a second aspect of the present invention, there is provided a clock period sensing circuit comprising: a plurality of delay circuits to which a clock signal is applied as a common input and which are arranged in parallel and have delay times that differ from one another; a plurality of latch circuits to which outputs of respective ones of the delay circuits are input for latching the clock signal as a latch timing signal; and a plurality of encoder circuits to which the outputs of the latch circuits are input for encoding information representing a boundary between delay circuits traversed by the clock signal and delay circuits not traversed by the clock signal, and outputting the encoded information as a control signal.
According to a third aspect of the present invention, the clock period sensing circuit is characterized in that the plurality of delay circuits have operating ranges that overlap each other slightly and centers of operation that differ from one another.
According to a fourth aspect of the present invention, the clock period sensing circuit is characterized in that each of the delay circuits has:
a P-type transistor which is connected between a power supply and an internal node and to which a signal obtained by inverting an input signal is applied as a gate input; and
an N-type transistor, which is driven by a constant-current source, connected between the internal node and ground and to which the signal obtained by inverting the input signal is applied as a gate input;
a plurality of serially connected switches and capacitors being connected in parallel between the internal node and ground, and delay time being decided by deciding a capacitance applied to the internal node by a capacitance control signal connected to a control terminal of each switch;
the delay circuit having an inverter for inverting and outputting a potential present at the internal node.
According to a fifth aspect of the present invention, there is provided a timing dividing circuit (interpolator) comprising:
first, second and third timing dividing circuit (interpolator)s connected in parallel and each having a P-type transistor which is connected between a power supply and an internal node and to which a signal obtained by taking NAND between first and second input signals is applied as a gate input, and first and second N-type transistors, which are driven by a constant-current source, connected between the internal node and ground and to which signals obtained by inverting the first and second input signals are applied as gate inputs; a plurality of serially connected switches and capacitors being connected in parallel between the internal node and ground, and delay time being decided by deciding a capacitance applied to the internal node by a capacitance control signal connected to a control terminal of each switch; each timing dividing circuit (interpolator) having an inverter for inverting and outputting a potential present at the internal node;
wherein a first clock of two clocks having different phases is supplied commonly as the first and second input signals to the first timing dividing circuit (interpolator);
first and second clocks constituting the two clocks having the different phases are supplied as the first and second input signals to the second timing dividing circuit (interpolator); and
a second clock of the two clocks having the different phases is supplied commonly as the first and second input signals to the third timing dividing circuit (interpolator);
the capacitance of the timing dividing circuit (interpolator) being selected by the control signal from the clock period sensing circuit according to any one of the first to fourth aspects.
According to a sixth aspect of the present invention, the timing dividing circuit (interpolator) is characterized in that the capacitance is set in such a manner that ranges over which the timing dividing circuit (interpolator) outputs a timing which is one-half the difference between the timings of the first and second clock inputs overlap each other along a time axis.
According to a seventh aspect of the present invention, there is provided a clock frequency multiplier circuit for outputting a frequency-multiplied clock, comprising:
a frequency dividing circuit for frequency-dividing a clock signal, generating and outputting a multiphase clock;
a clock period sensing circuit to which the clock signal is input;
a plurality of timing dividing circuits (interpolators) for outputting timing signals obtaining by dividing differences between input timings of the multiphase clock; and
multiplexer circuits for multiplexing outputs of the plurality of timing dividing circuits (interpolators);
wherein the clock period sensing circuit comprises the clock period sensing circuit according to any one of the first to fourth aspects.
According to an eighth aspect of the present invention, the clock frequency multiplier circuit is characterized in that each of the timing dividing circuits (interpolators) has:
a P-type transistor which is connected between a power supply and an internal node and to which a signal obtained by taking NAND between first and second input signals is applied as a gate input; and
first and second N-type transistors, which are driven by a constant-current source, connected between the internal node and ground and to which signals obtained by inverting the first and second input signals are applied as gate inputs;
a plurality of serially connected switches and capacitors being connected in parallel between the internal node and ground, and amount of delay being decided by deciding a capacitance applied to the internal node by a capacitance control signal connected to a control terminal of each switch;
each timing dividing circuit (interpolator) having an inverter for inverting and outputting a potential present at the internal node;
the capacitance being decided by a control signal from the clock period sensing circuit.
According to a ninth aspect, in the circuit according to the second aspect, each of said delay circuits has:
a first-type transistor which is connected between a power supply and an internal node and to which a signal indicative of an input signal is applied as a gate input; and
a second-type transistor, which is driven by a constant-current source, connected between said internal node and ground and to which the signal indicative of the input signal is applied as a gate input;
a plurality of serially connected switches and capacitors being connected in parallel between said internal node and ground, and delay time being decided by deciding a capacitance applied to said internal node by a capacitance control signal connected to a control terminal of each switch;
said delay circuit outputting an output signal indicative of a potential present at said internal node.
According to a tenth aspect, there is provided a timing dividing circuit (interpolator) comprising:
first, second and third timing dividing circuits (interpolators) connected in parallel and each having a first-type transistor which is connected between a power supply and an internal node and to which a signal obtained by taking logic between first and second input signals is applied as a gate input, and first and second-type transistors, which are driven by a constant-current source, connected between said internal node and ground and to which a signal obtained by inverting said signal obtained from the first and second input signals is applied as gate inputs; a plurality of serially connected switches and capacitors being connected in parallel between said internal node and ground, and delay time being decided by deciding a capacitance applied to said internal node by a capacitance control signal connected to a control terminal of each switch; each timing dividing circuit (interpolator) outputting an output signal indicative of a potential present at said internal node;
wherein a first clock of two clocks having different phases is supplied commonly as the first and second input signals to said first timing dividing circuit (interpolator);
first and second clocks constituting the two clocks having the different phases are supplied as the first and second input signals to said second timing dividing circuit (interpolator); and
a second clock of the two clocks having the different phases is supplied commonly as the first and second input signals to said third timing dividing circuit (interpolator);
the capacitance of said timing dividing circuit (interpolator) being selected by the control signal from the clock period sensing circuit according to the first aspect.